This invention relates generally to logic circuits of the type fabricated on a monolithic silicon semiconductor chip of an integrated circuit and more particularly, it relates to an output state protection network for a D-type master-slave flip-flop.
As it is well known, one form of flip-flop useful in digital logic applications is a D-type master-slave flip-flop which is sometimes referred to as an edge-triggered D-type flip-flop. Such a flip-flop has a single data input (D input), either one or a pair of complementary data outputs (Q or Q or both), and a clock input (CLK). In operation, data in the form of a logic level present at the data input (D input) is transferred to the data output (Q output) when the clock input CLK makes a specified clock pulse edge or transition (i.e. transition from logic "low" or "0" level to logic "high" or "1" level). If provided, complementary data output is available at the Q output. When the clock input CLK level changes from the high state to the low state, the logic state present at the D input prior to the clock transition is retained or latched at data output or outputs, regardless of subsequent changes in the data input until such time the clock input CLK makes a low-to-high transition again.
Such a typical prior art TTL D-type master-slave flip-flop is illustrated in FIG. 1 of the drawings and has been labeled "Prior Art". This flip-flop 10 is commercially available in integrated circuit form from Intel Corporation under a part No. designation of 88284. Typically, such a flip-flop may be included as but a small part of a much larger integrated circuit (i.e., large scale integration) in combination with either a variety of other types of digital logic elements and circuits or in combination with plurality of other similar D-type flip-flops.
As implied by the name of such a flip-flop, it is formed of two sections which are referred to in the art as a "master" section 12 and "slave" section 14. As can be seen, the data output Q is coupled by diode D801 to the base of a transistor Q804 and the complementary data output Q is coupled by diode D803 to the base of a transistor Q814 to form a toggle network so as to maintain the respective data outputs Q and Q in a stable state. For instance, when the data output Q is in a low state, the complementary data output Q will be forced to a high state through the diode D803. Accordingly, the data outputs Q and Q will remain in the same condition once the clock input CLK has been released. However, this toggle network arrangement suffers from a defect in that when a transient noise occurs at the data output which is in the high state this causes the high output to be pulled low. As a result, the other data output which is initially low will be forced to a high state because of the transient noise. Consequently, the flip-flop 10 will have its respective data outputs changed without any data input.
It would therefore be desirable to provide an output state protection network for toggling the data output node of a D-type master-slave flip-flop so the output node will be returned to its initial state after any transient noise has been removed from its output. As a result, the original data output has been protected from change in its state due to the transient noise.